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Category: Digital Logic Design Mcqs
Digital Logic Design Mcqs for Screening tests, Interviews, Viva and Other competitive exams. DLD Mcqs section will help users to prepare mcqs of DLD for various exams. Aspirants of Lecturer Computer Science, SST Computer Science, Subject Specialist Computer Science, Data Entry operator, Computer Programmer, Computer Operator, Software engineer and all other Competitive Exams can prepare their Digital Logic Design portion from here.
The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called__.
(A) Radiation-Erase programming method (REPM)
(B) In-System Programming (ISP)
(C) In-chip Programming (ICP)
(D) Electronically-Erase programming method(EEPM)
Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be __.
(A) Zero
(B) One
(C) Undefined
(D) No output as input is invalid
NAND gate is formed by connecting __.
(A) AND Gate and then NOT Gate
(B) NOT Gate and then AND Gate
(C) AND Gate and then OR Gate
(D) OR Gate and then AND Gate
The output of an XNOR gate is 1 when __ I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one.
(A) I Only
(B) IV Only
(C) I and IV only
(D) II and III only
Which is not characteristic of a shift register?
(A) Serial in/parallel in
(B) Serial in/parallel out
(C) Parallel in/serial out
(D)Parallel in/parallel out
In __ the Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop.
(A) Moore machine
(B) Meally machine
(C) Johnson counter
(D) Ring counter
A divide-by-50 counter divides the input __ signal to a 1 Hz signal.
(A) 10 Hz
(B) 50 Hz
(C) 100 Hz
(D) 500 Hz