(A) Enable input (EN) is set
(B) Preset input (PRE) is set
(C) Low-to-high transition of
(D) High-to-low transition of clock
Category: Digital Logic Design Mcqs
Digital Logic Design Mcqs for Screening tests, Interviews, Viva and Other competitive exams. DLD Mcqs section will help users to prepare mcqs of DLD for various exams. Aspirants of Lecturer Computer Science, SST Computer Science, Subject Specialist Computer Science, Data Entry operator, Computer Programmer, Computer Operator, Software engineer and all other Competitive Exams can prepare their Digital Logic Design portion from here.
In asynchronous digital systems all the circuits change their state with respect to a common clock?
(A) True
(B) False
(C) Both
(D) None
Demultiplexer converts __ data to __ data.
(A) Parallel data, serial data
(B) Serial data, parallel data
(C) Encoded data, decoded data
(D) All of the given options
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
(A) A > B = 1, A < B = 0, A < B = 1
(B) A > B = 0, A < B = 1, A = B = 0
(C) A > B = 1, A < B = 0, A = B = 0
(D) A > B = 0, A < B = 1, A = B = 1[showhide type="post" more_text="►Correct Option" less_text="Show less..."]
Correct Option is: C
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The output of an AND gate is one when __.
(A) All of the inputs are one
(B) Any of the input is one
(C) Any of the input is zero
(D) All the inputs are zero
3.3 v CMOS series is characterized by __ and __as compared to the 5 v CMOS series.
(A) Low switching speeds, high power dissipation
(B) Fast switching speeds, high power dissipation
(C) Fast switching speeds, very low power dissipation
(D) Low switching speeds, very low power dissipation
When the control line in tri-state buffer is high the buffer operates like a __gate.
(A) AND
(B) OR
(C) NOT
(D) XOR
Generally, the Power dissipation of __ devices remains constant throughout their operation.
(A) TTL
(B) CMOS 3.5 series
(C) CMOS 5 Series
(D) Power dissipation of all circuits increases with time