(A) Write Time
(B) Recycle Time
(C) Refresh Time
(D) Access Time
Category: Digital Logic Design Mcqs
Digital Logic Design Mcqs for Screening tests, Interviews, Viva and Other competitive exams. DLD Mcqs section will help users to prepare mcqs of DLD for various exams. Aspirants of Lecturer Computer Science, SST Computer Science, Subject Specialist Computer Science, Data Entry operator, Computer Programmer, Computer Operator, Software engineer and all other Competitive Exams can prepare their Digital Logic Design portion from here.
In __ Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register?
(A) Moore machine
(B) Meally machine
(C) Johnson counter
(D) Ring counter
A counter is implemented using three (3) flip-flops, possibly it will have __ maximum output status?
(A) 3
(B) 7
(C) 8
(D) 15
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by __.
(A) Using S-R Flop-Flop
(B) D-flipflop
(C) J-K flip-flop
(D) T-Flip-Flop
If S=1 and R=1, then Q(t+1) = __ for negative edge triggered flip-flop?
(A) 0
(B) 1
(C) Invalid
(D) Input is invalid
If S=1 and R=0, then Q(t+1) = __ for positive edge triggered flip-flop?
(A) 0
(B) 1
(C) Invalid
(D) Input is invalid
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO?
(A) THE FLOP-FLOP IS TRIGGERED
(B) Q=0 AND Q‟=1
(C) Q=1 AND Q’=0
(D) THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES?
(A) 2
(B) 4
(C) 6
(D) 8