(A) set
(B) reset
(C) invalid
(D) clear
Category: Digital Logic Design Mcqs
Digital Logic Design Mcqs for Screening tests, Interviews, Viva and Other competitive exams. DLD Mcqs section will help users to prepare mcqs of DLD for various exams. Aspirants of Lecturer Computer Science, SST Computer Science, Subject Specialist Computer Science, Data Entry operator, Computer Programmer, Computer Operator, Software engineer and all other Competitive Exams can prepare their Digital Logic Design portion from here.
The OR gate performs Boolean__.
(A) multiplication
(B) subtraction
(C) division
(D) addition
For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will__ if the clock goes HIGH?
(A) toggle
(B) set
(C) reset
(D) not change
The storage cell in SRAM is?
(A) a flip –flop
(B) a capacitor
(C) a fuse
(D) a magnetic domain
The 4-bit 2‟s complement representation of “+5” is__.
(A) 1010
(B) 1110
(C) 1011
(D) 0101
A GAL is essentially a__.
(A) Non-reprogrammable PAL
(B) PAL that is programmed only by the manufacturer
(C) Very large PAL
(D) Reprogrammable PAL
The alternate solution for a demultiplexer-register combination circuit is__.
(A) Parallel in / Serial out shift register
(B) Serial in / Parallel out shift register
(C) Parallel in / Parallel out shift register
(D) Serial in / Serial Out shift register
A synchronous decade counter will have __ flip-flops?
(A) 3
(B) 4
(C) 7
(D) 10