(A) Low-to-high transition of clock
(B) High-to-low transition of clock
(C) Enable input (EN) is set
(D) Preset input (PRE) is set
Category: Digital Logic Design Mcqs
Digital Logic Design Mcqs for Screening tests, Interviews, Viva and Other competitive exams. DLD Mcqs section will help users to prepare mcqs of DLD for various exams. Aspirants of Lecturer Computer Science, SST Computer Science, Subject Specialist Computer Science, Data Entry operator, Computer Programmer, Computer Operator, Software engineer and all other Competitive Exams can prepare their Digital Logic Design portion from here.
In order to synchronize two devices that consume and produce data at different rates, we can use __?
(A) Read Only Memory
(B) Fist In First Out Memory
(C) Flash Memory
(D) Fast Page Access Mode Memory
in __, all the columns in the same row are either read or written?
(A) Sequential Access
(B) MOS Access
(C) FAST Mode Page Access
(D) None of given options
A GAL is essentially a __?
(A) Non-reprogrammable PAL
(B) PAL that is programmed only by the manufacturer
(C) Very large PAL
(D) Reprogrammable PAL
A multiplexer with a register circuit converts __?
(A) Serial data to parallel
(B) Parallel data to serial
(C) Serial data to serial
(D) Parallel data to parallel
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop __?
(A) Doesn’t have an invalid state
(B) Sets to clear when both J = 0 and K = 0
(C) It does not show transition on change in pulse
(D) It does not accept asynchronous inputs
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)?
(A) 1100
(B) 0011
(C) 0000
(D) 1111
Stack is an acronym for__?
(A) FIFO memory
(B) LIFO memory
(C) Flash Memory
(D) Bust Flash Memory