(A) True
(B) False
(C) Both
(D) None
Category: Digital Logic Design Mcqs
Digital Logic Design Mcqs for Screening tests, Interviews, Viva and Other competitive exams. DLD Mcqs section will help users to prepare mcqs of DLD for various exams. Aspirants of Lecturer Computer Science, SST Computer Science, Subject Specialist Computer Science, Data Entry operator, Computer Programmer, Computer Operator, Software engineer and all other Competitive Exams can prepare their Digital Logic Design portion from here.
The divide-by-60 counter in digital clock is implemented by using two cascading counters?
(A) Mod-6, Mod-10
(B) Mod-50, Mod-10
(C) Mod-10, Mod-50
(D) Mod-50, Mod-6
In a sequential circuit the next state is determined by __ and __?
(A) State variable, current state
(B) Current state, flip-flop output
(C) Current state and external input
(D) Input and clock signal applied
A 8-bit serial in / parallel out shift register contains the value “8”, __ clock signal(s) will be required to shift the value completely out of the register?
(A) 1
(B) 2
(C) 4
(D) 8
The minimum time for which the input signal has to be maintained at the input of flip-flop is called __ of the flip-flop.
(A) Set-up time
(B) Hold time
(C) Pulse Interval time
(D) Pulse Stability time (PST)
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
(A) True
(B) False
The divide-by-60 counter in digital clock is implemented by using two cascading counters:
(A) Mod-6, Mod-10
(B) Mod-50, Mod-10
(C) Mod-10, Mod-50
(D) Mod-50, Mod-6
In a sequential circuit the next state is determined by __ and __.
(A) State variable, current state
(B) Current state, flip-flop output
(C) Current state and external input
(D) Input and clock signal applied