(A) 30
(B) 100
(C) 1000
(D) 0000
Category: Digital Logic Design Mcqs
Digital Logic Design Mcqs for Screening tests, Interviews, Viva and Other competitive exams. DLD Mcqs section will help users to prepare mcqs of DLD for various exams. Aspirants of Lecturer Computer Science, SST Computer Science, Subject Specialist Computer Science, Data Entry operator, Computer Programmer, Computer Operator, Software engineer and all other Competitive Exams can prepare their Digital Logic Design portion from here.
Divide-by-160 counter is acheived by using?
(A) Flip-Flop and DIV 10
(B) Flip-Flop and DIV 16
(C) DIV 16 and DIV 32
(D) DIV 16 and DIV 10
A flip-flop is presently in SET stae and must remain SET on the next cliock pulse. What must j and K be?
(A) J = 1, K = 0
(B) J = 1, K = X(Don’t care)
(C) J = X(Don’t care), K = 0
(D) J = 0, K = X(Don’t care)
For a gated D-Latch if EN=1 and D=1 then Q(t+1) = __.
(A) 0
(B) 1
(C) Q(t)
(D) Invalid
A decade counter can be implemented by truncating the counting sequence of a MOD-20 counter?
(A) True
(B) False
(C) Both
(D) None
In case of cascading Integrated Circuit counters, the enable inputs and RCOof the Integrated Circuit counters allow cascading of multiple counters together?
(A) True
(B) False
(C) Both
(D) None
The terminal count of a 4-bit binary counter in the DOWN mode is__.
(A) 0000
(B) 0011
(C) 1100
(D) 1111
A mono-stable device only has a single stable state?
(A) True
(B) False
(C) Both
(D) None