(A) (n raise to power 2)
(B) (n raise to power 2 and then minus 1)
(C) 2 raise to power n)
(D) (2 raise to power n and then minus 1)
Category: Digital Logic Design Mcqs
Digital Logic Design Mcqs for Screening tests, Interviews, Viva and Other competitive exams. DLD Mcqs section will help users to prepare mcqs of DLD for various exams. Aspirants of Lecturer Computer Science, SST Computer Science, Subject Specialist Computer Science, Data Entry operator, Computer Programmer, Computer Operator, Software engineer and all other Competitive Exams can prepare their Digital Logic Design portion from here.
The terminal count of a 4-bit binary counter in the UP mode is__.
(A) 1100
(B) 0011
(C) 1111
(D) 0000
The Synchronous counters are also known as Ripple Counters?
(A) True
(B) False
(C) Both
(D) None
The counter states or the range of numbers of a counter is determined by the formula. “n” represents the total number of flip-flops)?
(A) (n raise to power 2)
(B) (n raise to power 2 and then minus 1)
(C) (2 raise to power n)
(D) (2 raise to power n and then minus 1)
When the both inputs of edge-triggered J-K flop-flop are set to logic zero __.
(A) The flop-flop is triggered
(B) Q=0 and Q’=1
(C) Q=1 and Q’=0
(D) The output of flip-flop remains unchanged
Bi-stable devices remain in either of their __ states unless the inputs force the device to switch its state.
(A) 10
(B) 8
(C) 3
(D) 2
If S=1 and R=0, then for positive edge triggered flip-flop Q(t+1) = __ Select correct option.
(A) 0
(B) 1
(C) Invalid
(D) Input is invalid
The power consumed by a flip-flop is defined by __.
(A) P = Icc x Rcc
(B) P = Vcc x Rcc
(C) P = Vcc x Icc
(D) P = Mcc x Vcc