(A) Parallel in / Serial out shift register
(B) Serial in / Parallel out shift register
(C) Parallel in / Parallel out shift register
(D) Serial in / Serial Out shift register
Category: Digital Logic Design Mcqs
Digital Logic Design Mcqs for Screening tests, Interviews, Viva and Other competitive exams. DLD Mcqs section will help users to prepare mcqs of DLD for various exams. Aspirants of Lecturer Computer Science, SST Computer Science, Subject Specialist Computer Science, Data Entry operator, Computer Programmer, Computer Operator, Software engineer and all other Competitive Exams can prepare their Digital Logic Design portion from here.
In __ outputs depend only on the current state.
(A) Mealy machine
(B) Moore Machine
(C) State Reduction table
(D) State Assignment table
A transparent mode means __.
(A) The changes in the data at the inputs of the latch are seen at the output
(B) The changes in the data at the inputs of the latch are not seen at the output
(C) Propagation Delay is zero (Output is immediately changed when clock signal is applied)
(D) Input Hold time is zero (no need to maintain input after clock transition)
RCO Stands for __.
(A) Reconfiguration Counter Output
(B) Reconfiguration Clock Output
(C) Ripple Counter Output
(D) Ripple Clock Output
The low to high or high to low transition of the clock is considered to be a(n)__.
(A) State
(B) Edge
(C) Trigger
(D) One-shot
If the S and R inputs of the gated S-R latch are connected together using a __gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch).
(A) AND
(B) OR
(C) NOT
(D) XOR
3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions?
(A) True
(B) False
(C) Both
(D) None
The __ Encoder is used as a keypad encoder.
(A) 2-to-8 encoder
(B) 4-to-16 encoder
(C) BCD-to-Decimal
(D) Decimal-to-BCD Priority