(A) n to 2n
(B) (n-1) to 2n
(C) (n-1) to (2n-1)
(D) n to 2n-1
Category: Digital Logic Design Mcqs
Digital Logic Design Mcqs for Screening tests, Interviews, Viva and Other competitive exams. DLD Mcqs section will help users to prepare mcqs of DLD for various exams. Aspirants of Lecturer Computer Science, SST Computer Science, Subject Specialist Computer Science, Data Entry operator, Computer Programmer, Computer Operator, Software engineer and all other Competitive Exams can prepare their Digital Logic Design portion from here.
The output of an XOR gate is zero (0) when __ I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one.
(A) I Only
(B) IV Only
(C) I and IV only
(D) II and III only
Caveman number system is Base __ number system.
(A) 2
(B) 5
(C) 10
(D) 16
Q2 :=Q1 OR X OR Q3 The above ABEL expression will be?
(A) Q2:= Q1 $ X $ Q3
(B) Q2:= Q1 # X # Q3
(C) Q2:= Q1 & X & Q3
(D) Q2:= Q1 ! X ! Q3
If the FIFO Memory output is already filled with data then__.
(A) It is locked; no data is allowed to enter
(B) It is not locked; the new data overwrites the previous data
(C) Previous data is swapped out of memory and new data enters
(D) None of given options
In the following statement( Z PIN 20 ISTYPE „reg.invert‟;) The keyword “reg.invert” indicates __.
(A) An inverted register input
(B) An inverted register input at pin 20
(C) Active-high Registered Mode output
(D) Active-low Registered Mode output
In __ outputs depend only on the combination of current state and inputs.
(A) Mealy machine
(B) Moore Machine
(C) State Reduction table
(D) State Assignment table
For a gated D-Latch if EN=1 and D=1 then Q(t+1) =__.
(A) 0
(B) 1
(C) Q(t)
(D) Invalid