(A) two AND gates, two OR gates, two inverters
(B) three AND gates, two OR gates, one inverter
(C) two AND gates, one OR gate, two inverters
(D) two AND gates, one OR gate
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(A) two AND gates, two OR gates, two inverters
(B) three AND gates, two OR gates, one inverter
(C) two AND gates, one OR gate, two inverters
(D) two AND gates, one OR gate