(A) Using S-R Flop-Flop
(B) D-flipflop
(C) J-K flip-flop
(D) T-Flip-Flop
Tag: Digital Logic Design Solved Mcqs
If S=1 and R=1, then Q(t+1) = __ for negative edge triggered flip-flop?
(A) 0
(B) 1
(C) Invalid
(D) Input is invalid
If S=1 and R=0, then Q(t+1) = __ for positive edge triggered flip-flop?
(A) 0
(B) 1
(C) Invalid
(D) Input is invalid
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO?
(A) THE FLOP-FLOP IS TRIGGERED
(B) Q=0 AND Q‟=1
(C) Q=1 AND Q’=0
(D) THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES?
(A) 2
(B) 4
(C) 6
(D) 8
Sum term (Max term) is implemented using __ gates?
(A) OR
(B) AND
(C) NOT
(D) OR-AND
In designing any counter the transition from a current state to the next sate is determined by?
(A) Current state and inputs
(B) Only inputs
(C) Only current state
(D) current state and outputs
The 3-variable Karnaugh Map (K-Map) has __ cells for min or max terms?
(A) 4
(B) 8
(C) 12
(D) 16