(A) Current state and the inputs
(B) Current state and outputs
(C) Previous state and inputs
(D) Previous state and outputs
Tag: Digital Logic Design Solved Mcqs
__occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay?
(A) Race condition
(B) Clock Skew
(C) Ripple Effect
(D) None of given options
__ is one of the examples of synchronous inputs?
(A) J-K input
(B) EN input
(C) Preset input (PRE)
(D) Clear Input (CLR)
Addition of two octal numbers “36” and “71” results in__?
(A) 213
(B) 123
(C) 127
(D) 345
LUT is acronym for __ Look Up Table?
(A) Local User Terminal
(B) Least Upper Time Period
(C) Look Up Table
(D) None of given options
The voltage gain of the Inverting Amplifier is given by the relation __?
(A) Vout / Vin = – Rf / Ri
(B) Vout / Rf = – Vin / Ri
(C) Rf / Vin = – Ri / Vout
(D) Rf / Vin = Ri / Vout
Excess-8 code assigns __ to “-8”?
(A) 1110
(B) 1100
(C) 1000
(D) 0000
In asynchronous transmission when the transmission line is idle, __?
(A) It is set to logic low
(B) It is set to logic high
(C) Remains in previous state
(D) State of transmission line is not used to start transmission