(A) Mod-3 counter
(B) Mod-5 counter
(C) Mod-8 counter
(D) Mod-10 counter
Tag: Digital Logic Design Solved Mcqs
The __ input overrides the __ input?
(A) Asynchronous, synchronous
(B) Synchronous, asynchronous
(C) Preset input (PRE), Clear input (CLR)
(D) Clear input (CLR), Preset input (PRE)
__ is said to occur when multiple internal variables change due to change in one input variable?
(A) Clock Skew
(B) Race condition
(C) Hold delay
(D) Hold and Wait
74HC163 has two enable input pins which are __ and?
(A) ENP, ENT
(B) ENI, ENC
(C) ENP, ENC
(D) ENT, ENI
The minimum time for which the input signal has to be maintained at the input of flip-flop is called __ of the flip-flop?
(A) Set-up time
(B) Hold time
(C) Pulse Interval time
(D) Pulse Stability time (PST)
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained?
(A) True
(B) False
(C) Both
(D) None
The divide-by-60 counter in digital clock is implemented by using two cascading counters?
(A) Mod-6, Mod-10
(B) Mod-50, Mod-10
(C) Mod-10, Mod-50
(D) Mod-50, Mod-6
In a sequential circuit the next state is determined by __ and __?
(A) State variable, current state
(B) Current state, flip-flop output
(C) Current state and external input
(D) Input and clock signal applied