Tag: DLD Mcqs

(A) AND
(B) OR
(C) NAND
(D) XOR

(A) 2 INPUTS AND 1 OUTPUT
(B) 2 INPUTS AND 2 OUTPUT
(C) 3 INPUTS AND 1 OUTPUT
(D) 3 INPUTS AND 2 OUTPUT

(A) OR Gate and then NOT Gate
(B) NOT Gate and then OR Gate
(C) AND Gate and then OR Gate
(D) OR Gate and then AND Gate

(A) 0000
(B) 1001
(C) 1000
(D) 1111

(A) Bit
(B) Nibble
(C) Byte
(D) Word

(A) Parallel in / Serial out shift register
(B) Serial in / Parallel out shift register
(C) Parallel in / Parallel out shift register
(D) Serial in / Serial Out shift register

(A) Mealy machine
(B) Moore Machine
(C) State Reduction table
(D) State Assignment table

(A) The changes in the data at the inputs of the latch are seen at the output
(B) The changes in the data at the inputs of the latch are not seen at the output
(C) Propagation Delay is zero (Output is immediately changed when clock signal is applied)
(D) Input Hold time is zero (no need to maintain input after clock transition)