(A) AND Gate and then NOT Gate
(B) NOT Gate and then AND Gate
(C) AND Gate and then OR Gate
(D) OR Gate and then AND Gate
Tag: DLD Mcqs
The output of an XNOR gate is 1 when __ I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one.
(A) I Only
(B) IV Only
(C) I and IV only
(D) II and III only
Which is not characteristic of a shift register?
(A) Serial in/parallel in
(B) Serial in/parallel out
(C) Parallel in/serial out
(D)Parallel in/parallel out
In __ the Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop.
(A) Moore machine
(B) Meally machine
(C) Johnson counter
(D) Ring counter
A divide-by-50 counter divides the input __ signal to a 1 Hz signal.
(A) 10 Hz
(B) 50 Hz
(C) 100 Hz
(D) 500 Hz
A negative edge-triggered flip-flop changes its state when?
(A) Enable input (EN) is set
(B) Preset input (PRE) is set
(C) Low-to-high transition of
(D) High-to-low transition of clock
In asynchronous digital systems all the circuits change their state with respect to a common clock?
(A) True
(B) False
(C) Both
(D) None
Demultiplexer converts __ data to __ data.
(A) Parallel data, serial data
(B) Serial data, parallel data
(C) Encoded data, decoded data
(D) All of the given options