(A) AND gate, Resistor, Capacitor and NOT Gate
(B) NAND gate, Resistor, Capacitor and NOT Gate
(C) NOR gate, Resistor, Capacitor and NOT Gate
(D) XNOR gate, Resistor, Capacitor and NOT Gate
Tag: DLD Mcqs
occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay?
(A) Race condition
(B) Clock Skew
(C) Ripple Effect
(D) None of given options
A synchronous decade counter will have __ flip-flops.
(A) 3
(B) 4
(C) 7
(D) 10
In designing any synchronous counter a modulus number is used which determine the number of __ used in a counter.
(A) Registers
(B) Flip Flops
(C) Counters
(D) Latches
The 74HC163 is a 4-bit Synchronous Counter.it has __ parallel data inputs pins.
(A) 2
(B) 4
(C) 6
(D) 8
The counter states or the range of numbers of a counter is determined by the formula. (“n” represents the total number of flip-flops)?
(A) (n raise to power 2)
(B) (n raise to power 2 and then minus 1)
(C) 2 raise to power n)
(D) (2 raise to power n and then minus 1)
The terminal count of a 4-bit binary counter in the UP mode is__.
(A) 1100
(B) 0011
(C) 1111
(D) 0000
The Synchronous counters are also known as Ripple Counters?
(A) True
(B) False
(C) Both
(D) None